LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Invert12 IS
   PORT(
		hurr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
		durr : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
       );
END Invert12;

ARCHITECTURE invert12_arch OF Invert12 IS


COMPONENT CLA12 IS
	PORT( a,b				:IN 	STD_LOGIC_VECTOR(11 DOWNTO 0);
		  output			:OUT	STD_LOGIC_VECTOR(11 DOWNTO 0));
END COMPONENT;

SIGNAL tempinvert : STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL loneliest : STD_LOGIC_VECTOR(11 DOWNTO 0);

BEGIN

loneliest <= "000000000001";

tempinvert(0) <= NOT(hurr(0));
tempinvert(1) <= NOT(hurr(1));
tempinvert(2) <= NOT(hurr(2));
tempinvert(3) <= NOT(hurr(3));
tempinvert(4) <= NOT(hurr(4));
tempinvert(5) <= NOT(hurr(5));
tempinvert(6) <= NOT(hurr(6));
tempinvert(7) <= NOT(hurr(7));
tempinvert(8) <= NOT(hurr(8));
tempinvert(9) <= NOT(hurr(9));
tempinvert(10) <= NOT(hurr(10));
tempinvert(11) <= NOT(hurr(11));

DoMath: CLA12 PORT MAP (tempinvert, loneliest, durr);

   
END invert12_arch;